1. Field of the Invention
The present invention relates to an effective address pre-calculation type pipelined microprocessor, and more specifically, to a mechanism for avoiding a register hazard generated at the time of the effective address pre-calculation.
2. Description of Related Art
In the prior art, some large-sized computers operating in a pipelined manner comprise copy registers provided in an effective address calculation unit or an instruction decoder unit for the purpose of copying contents of all general purpose registers. In these large-sized computers, when an instruction for changing a content of some general purpose register is decoded, the effective address calculation unit or the instruction decoder unit estimates the result of execution of the instruction, and updates a value of a copy register holding the copy of the general purpose register. When a general purpose register is used as a base register for the register indirect addressing, the copy register copying the general purpose register is used as the base register, so that a register hazard which would be generated in the effective address pre-calculation is avoided.
However, if the above mentioned arrangement is adopted, the hardware inevitably becomes vary large. Because of this reason, a microprocessor which adopts the same effective address pre-calculation type pipelined system cannot adopt the above mentioned arrangement for the large-sized computer. As a result, the effective address precalculation type pipelined microprocessor cannot avoid the register hazard in the case that a general purpose register which can be modified in accordance with an auto-modification addressing in a preceding instruction is used in a register indirect addressing in a succeeding instruction.
For example, there is known an addressing mode in which a base address register value is addressed as an operand address, and thereafter, when an instruction is executed, the base address register value is incremented or decremented by an amount corresponding to the data size. This mode is called a "post-modification addressing" hereinafter. There is also known an addressing mode in which the base address register value is added with or subtracted by the amount corresponding to the data size so that the result of the addition or subtraction is used as the operand address, and when an instruction is executed, the base address register value is written with the result of the addition or subtraction of the data size. This mode is called "pre-modification addressing" hereinafter. The post-modification addressing and the pre-modification addressing are collectively called an "auto-modification addressing" hereinafter. If a general register designated to be modified in the auto-modification addressing in a preceding instruction is used as a base address register in a succeeding instruction before it is actually modified by an instruction execution unit, a so-called register hazard occurs, and an address generation for the succeeding instruction cannot be executed until execution of the preceding instruction having the preceding auto-modification addressing has been completed. As a result, the pipelined operation stops in the stage for the effective address calculation. Namely, a job opening occurs in the pipelined operation.